The invention relates to formal analysis and verification of computer systems.
Multi-threading is a well-known and pervasive technique for extracting performance from a computer system by exploiting parallelism among its different components. Unfortunately, the many possible interleavings among the local operations of individual threads makes multi-threaded software behaviorally complex and difficult to analyze. It would be advantageous to apply formal methods to debug such systems, but existing techniques for verifying concurrent programs suffer from various drawbacks. Some prior art schemes do not scale to large programs due to the state space explosion problem. Some techniques such as thread modular model checking are not guaranteed complete, thus resulting in possible bogus error traces. Other prior art techniques rely on manual and hence time-consuming abstractions to compress the state space enough to make verification amenable.
In co-pending commonly-assigned U.S. Utility patent application Ser. No. 11/174,791, the contents of which are incorporated by reference, a new model checking technique was disclosed which reduces the problem of correctness of a concurrent program comprised of multiple threads communicating via locks to one concerned with verifying augmented versions of each individual thread. It would be advantageous to extend the technique disclosed therein to a broad range of correctness properties, e.g., as expressed using full-blown temporal logic.